1. Field of the Invention
The present invention generally relates to a successive approximation register (SAR) ADC, and more particularly to a successive approximation ADC for increasing conversion rate by a direct switching technique for capacitor array through comparator output and method thereof.
2. Description of Related Art
FIG. 1 illustrates a conventional 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). As shown in FIG. 1, SAR ADC 1 includes two symmetrical digital to analog converters (DACs) 11, 13 which both consist of a capacitor array (C9 to C0) with binary weighted values. In operation, a comparator 15 first samples and compares the differential input voltages Vip, Vin, and a SAR control logic (“SAR”) 17 switches the switches SP9, SN9 to control the terminal voltages on. the terminals of the capacitors C9 based on a comparison result of the comparator 15. Due to the change of the terminal voltages, the redistributed charges generate new voltages on the two terminals of the DACs 11, 13. Then, the comparator 15 compares the outputs of the DACs 11, 13 sequentially, and the SAR 17 converts the corresponding digital bits (B1 to B10) based on the comparison result of the comparator 15.
Specifically, the SAR 17 traditionally comprises a logic circuit 171 which receives and calculates the comparison results outp, outn from the comparator 15 to determine the voltage level of the switches SPi, SNi in each comparison phase. FIG. 2 illustrates a conventional logic circuit for controlling the switches. As shown in FIG. 2, the generated comparison results outp, outn in each comparison. phase must be calculated through at least one NAND gate 1711, two D-FF 1712, 1713, and one AND gate 1714, then the signal which control the switches SP9, SN9 can be obtained. The nature delay of the above digital logic gates may spend a lot of time, and it must determine how to switch the next switches SPi, SNi via the logic circuit 171 after converting each digital bit. The more the number of converting bits of the ADC is, the larger the generated delay is, so that the conversion time in overall SAR ADC system may be greatly increased.
Therefore, with IC design, a need has arisen to propose a novel circuit which can decrease conversion time of the digital bits, so as to enable the designed circuit to achieve high conversion rate and performance.